Method and apparatus for error correction

Details Method and apparatus for error correction Method and apparatus for error correction

1988-02-16

1989-12-05

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

048857505

ABSTRACT:
A digital signal has frames each composed of n data words and a parity code. One data word has m bits. The letters n and m represent natural numbers equal to or greater than 2. One frame of data words is written into a memory. When writing of one frame of the data words into the memory is completed, a write end flag is generated and written in the memory. After the detection of the write end flag, the data words are read out from the memory. An error is detected from the read data words and is corrected.

REFERENCES:
patent: 4175692 (1979-11-01), Watanabe
patent: 4359771 (1982-11-01), Johnson et al.
patent: 4712216 (1987-12-01), Glaise
patent: 4788685 (1988-11-01), Sako et al.

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