Three level poly dynamic ram with poly bit lines

Details Three level poly dynamic ram with poly bit lines Three level poly dynamic ram with poly bit lines

1981-01-23

1983-12-06

Larkins, William D.

357 41, 357 59, 357 71, H01L 2710, H01L 2350, G11C 1140

Patent

active

044196822

ABSTRACT:
First polycrystalline silicon layers are insulatively disposed over a p-type semiconductor substrate. Second polycrystalline silicon layers are formed on the substrate adjacent to the first polycrystalline silicon layers. Third polycrystalline silicon layers are insulatively disposed over the substrate between the first polycrystalline silicon layers and the second polycrystalline silicon layers. The third polycrystalline silicon layers function as gates of MOS transistors, and the first polycrystalline silicon layers function as capacitors in cooperation with the substrate. The second polycrystalline silicon layers function as the digit lines, and are so formed as to alternately contact substrate and pass over the first polycrystalline silicon layers insulated therefrom by thick insulative layers.

REFERENCES:
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patent: 4060796 (1977-11-01), Togei et al.
patent: 4115795 (1978-09-01), Masuoka et al.
patent: 4131906 (1978-12-01), Kinoshita
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patent: 4262298 (1981-04-01), Tuan et al.
patent: 4291322 (1981-09-01), Clemens et al.
patent: 4334236 (1982-06-01), Hoffmann et al.
Chatterjee et al., "A Survey of High-Density Dynamic RAM Cell Concepts", IEEE Transactions on Electron Devices 827-839 (Jun. 1979).

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