Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Patent
1995-07-03
2000-07-18
Teska, Kevin J.
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
39550007, 39550013, G06F 1750
Patent
active
060901500
ABSTRACT:
In laying out the wiring of an LSI, PWB or the like, based on the logical connection information, layout result information, delay analyzing information or the like, the delay time margins for the entire path is evaluated by means of a delay analyzing means to detect a worst case path having the worst delay time margin from among the delay time margins for each path by means of a worst case path detecting means. A difference between the delay time margin of a secondary worst case path having the worst delay time margin among the next stage paths of this worst case path and the delay time margin of the preceding worst case path is evaluated by means of a clock skew adjusting time extracting means. Within the range of this clock skew adjusting time, an optimum delay time to be added is calculated by means of an additional delay time calculating means. A delay gate is inserted in the middle of the clock net for logical change by means of delay gate inserting means so that the calculated delay time is added to the clock net leading to the cock input terminal of the flip-flop at the terminal side of the worst case path.
REFERENCES:
patent: 4263651 (1981-04-01), Donath et al.
patent: 4642890 (1987-02-01), Hechtman et al.
patent: 4694403 (1987-09-01), Nomura
patent: 4698760 (1987-10-01), Lembach et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5168455 (1992-12-01), Hooper
patent: 5191541 (1993-03-01), Laudman et al.
patent: 5208764 (1993-05-01), Rusu et al.
patent: 5410491 (1995-04-01), Minami
Hitchock, Sr. et al., "Timing Analysis of Computer Hardware," IBM J. of Res. & Dev., Jan. 1982, pp. 100-105.
Hitchcock, Sr. et al., "Timing Analysis of Computer Hardware", IBM J. Res Dev., vol. 26, No. 1, Jan. 1982.
Cho et al., "A Buffer Distribution Algorithm for High Performance Clock Net Optimization," IEEE, 1995, pp. 84-97.
Kahng, et al., "High-Performance Clock Routing Based on Recursive Geometric Matching", 28th ACM/IEEE Design Automation Conference, 1991, pp. 322-327.
NEC Corporation
Phan Thai
Teska Kevin J.
LandOfFree
Method of designing clock wiring and apparatus for implementing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of designing clock wiring and apparatus for implementing , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of designing clock wiring and apparatus for implementing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2031959