Multiprocessor system with cascaded modules combining processors

Details Multiprocessor system with cascaded modules combining processors Multiprocessor system with cascaded modules combining processors

1993-01-14

1995-11-07

Lim, Krisna

Boots, shoes, and leggings

364137, 3642285, 364229, 3642381, 3642382, 3642383, 364DIG1, G06F 1516

Patent

active

054653754

ABSTRACT:
In a multiprocessor data processing system, modules are cascaded by means of intermodule buses. Each module comprises a data processing unit, a first memory, a logic cell array programmable into four input/output interfaces, a second memory and a specialized processing unit such as a digital signal processor (DSP). A first interface, the first memory and the data processing unit are interconnected by a module bus. A fourth interface, the second memory and the specialized processing unit are interconnected by another module bus. A feedback bus connects the second and third interfaces in the last and first modules for constituting a ring. Such a system is particularly intended for image recognition, such as digitalized handwritten digits for postal distribution.

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S. Y. Kung et al., "Parallel Architectures for Artificial Neural Nets"; IEEE International Conference on Neural Networks, San Diego, Calif. Jul. 24-27, 1988, 8 pages.

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