Boots – shoes – and leggings
Patent
1993-06-10
1995-11-07
Bowler, Alyssa H.
Boots, shoes, and leggings
395406, 395375, 395650, 39520008, 395479, 3642281, 3642282, 3642321, 36424294, 3642474, 364DIG1, G06F 1300
Patent
active
054653690
DESCRIPTION:
BRIEF SUMMARY
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a national phase of PCT/RO 92 00005 files 12 Mar. 1992 and based, in turn, on Romania national application 148526 filed 10 Oct. 1991 under the International Convention.
1. Field of the Invention
The invention relates to a network for parallel processing of logic programs intended to provide a highly parallel processing system to be used in fields in which data processing performances should be very high.
2. Background of the Invention
High performances in data processing have been obtained with parallel processing whereby the processing processes are decomposed into components distributed among concurrently operating equipement. Among the well-known parallel processing structures are: the pipeline architecture and multiprocessor architecture (Bell,C. G., Newell, A.--Computer structures: reading and exemples, McGraw-Hill Book Comp., New York, 1971; Treleaven, P., Vanneski, M.--Future parallel computers, Springer Verlag, Berlin, 1987).
The pipelining procedure is an approach to parallel processing at the instructions bit level: Instruction are analyzed and decomposed into constituent operations and then each of the operations is executed on dedicated serially connected units. The output of a preceeding unit s taken over by the subsequent unit which, after having executed the appropriate operations, transfers the output to the next unit. (Chen, T. C.--Parallelism, pipelining and computer efficiency, Computer Design, January 1971).
Well-known systems have benefitted from such a structure for increasing their performances (Flores, I.--Lookahead control in the IBM System 370/165, Computer no. 11, vol. 7, Nov. 1974; Thornton, I. E.--Parallel operation in the Control Data 6600, AFIPS Proc. FJCC, part. 2, vol. 26, 1964, pp.34-40).
However, pipeline structures are sometimes inefficient because the large percentage of branch instructions (about 25%) frequently slows down the pace further the line should be emptied of those instructions which had previously been taken from memory. The interrelations between instructions often cause deadlocks in processing. With different servicing time for the constituient units of the connecting line the only way of rendering the line throughput uniform is to use several units installed at one line node for parallel operations which makes control difficult. Also on the interrelations between instructions often does not allow an efficient use of the units installed to run in parallel. Given the complexity and the temporal character of the instructions, a range of few cycles to tens of cycles, their lack in uniformity bears on the performance of the equipment and complicates its supervision. The method best applies to those systems where processing is highly uniform (vector processing, array processing, image processing, etc.) and is mainly associated with supercomputers (Weiss, S., Smith, J. E.--Instruction issue logic in pipe-linead supercomputers, IEEE Trans. on Comp., C-33, no. 11, Nov. 1984).
Parallel processing with several processors of which interconnection is made by one of the well-known methods (Zakharov, V.--Parallelism and array processing, IEEE Trans. on Comp., Jan. 1984; Georgescu, I.--Communication in parallel processing systems, Studies and Researches in Computer and Informatics, vol. 1, no. 1, March 1990): shared memory (common bus, crossbar switch) or network (tree, ring, array, hypercube, etc.) is characterized by the fact that a plurality of stand-alone processors, each of them processing an individual job, are connected in a geometrical configuration. A common bus connection of several processors to a memory limits the configuration to that bus throughput, thus making it a critical point of the structure. As to those configurations that make use of a crossbar switch, enabling the access of each processor to each memory module, they have the handicap of a complex interconnection system, the complexity of which increases with the product of the number of connected devices. With different types of networks
REFERENCES:
patent: 4720784 (1988-01-01), Radharkrishnan
patent: 5043870 (1991-08-01), Ditzel et al.
patent: 5129077 (1992-07-01), Hillis
patent: 5136717 (1992-08-01), Morley et al.
patent: 5157778 (1992-10-01), Bischoff et al.
"Communication in Parallel Processing Systems" by I. Georgescu, Studi and Research in Computers & Informatics, vol. 1, No. 1, Mar. 1990.
Bowler Alyssa H.
Dubno Herbert
Harrity John
LandOfFree
Network structure for parallel software processing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Network structure for parallel software processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Network structure for parallel software processing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-202882