Full duplex bit synchronous data rate buffer

Details Full duplex bit synchronous data rate buffer Full duplex bit synchronous data rate buffer

1978-11-20

1980-10-21

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 85, 370 91, 340347DD, H04J 316

Patent

active

042298156

ABSTRACT:
The disclosed full duplex bit synchronous data rate buffer (15) adapts high speed burst data signals for transmission over low speed data facilities. The data rate buffer (15) includes a buffer control circuit (201-205, 105) for interactively controlling a first data buffer (101) for down-converting the high speed signals (107) to low speed signals (109) and a second data buffer (102) for up-converting low speed data signals (108) to high speed burst data signals (106). The data rate buffer (15) accepts random changes in the length of each high speed burst data signal without a loss in bit synchronism and adjusts for changes in the number of burst data signals contained in each frame.

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patent: 3480734 (1969-11-01), Kuroyanagi et al.
patent: 3534264 (1970-10-01), Blasbalg et al.
patent: 3772653 (1973-11-01), Brown
patent: 3825899 (1974-07-01), Haeberle
patent: 4046972 (1977-09-01), Huizinga
patent: 4048440 (1977-09-01), Peck
patent: 4063041 (1977-12-01), Vollnhals
patent: 4138596 (1979-02-01), Roche
"Fifo", Progress, vol. 1, No. 4, Fairchild Camera Technical Journal T-46-01, Sep. 1974.
Bell System Tech. Journal, vol. 54, No. 5, May-Jun. 1975, "Local Distribution System", p. 919 et seq.
Bell System Tech. Journal, Jan. 1962, vol. 41, p. 25 et seq., "A Bipolar Repeater for Pulse Code Modulation Signals".

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