Round off correction logic for modified Booth's algorithm

Details Round off correction logic for modified Booth's algorithm Round off correction logic for modified Booth's algorithm

1978-12-06

1980-10-21

Smith, Jerry

Boots, shoes, and leggings

364757, 364758, G06F 752

Patent

active

042298008

ABSTRACT:
A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the multiplier for rounding its final product off to a predetermined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off.

REFERENCES:
patent: 3290493 (1966-12-01), Githens, Jr. et al.
patent: 3878985 (1975-04-01), Ghest et al.
patent: 3885141 (1975-05-01), Kieburtz
patent: 4153938 (1979-05-01), Ghest et al.
S. Waser, "High-Speed Monolithic Multipliers for Real-Time _Digital Signal Processing", Computer, Oct. 1978, pp. 19-29.

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