MOSFET Fabrication process for reducing overlap capacitance and

Details MOSFET Fabrication process for reducing overlap capacitance and MOSFET Fabrication process for reducing overlap capacitance and

1981-08-07

1984-05-01

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29591, 148187, H01L 2122, H01L 2128

Patent

active

044452667

ABSTRACT:
A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors on P-type semiconductor substrate (10). A layer of oxide (14) is formed on the substrate (10) and then a polysilicon layer (16) is formed on top of the oxide layer (14). A layer of silicon nitride (18) is deposited on top of the polysilicon layer (16). The silicon nitride layer (18), polysilicon layer (16) and oxide layer (14) are selectively etched to form a conductor pattern. The conductor pattern defines a gate electrode and a plurality of interconnecting lines (42) that interconnect transistors to each other and to the peripheral circuits that drive the transistors. The source and drain regions (26 and 28) are ion implanted with arsenic ions. The exposed sidewalls of the polysilicon layer (16) are oxidized lateral and subjacent to the silicon nitride layer (18). The oxidation forms a lateral band of oxide (32) on the polysilicon layer (16) and effectively reduces the conductive width of the polysilicon layer (16). The reduced conductive width reduces the overlap capacitance. The silicon nitride layer (18) is then removed and a layer of tungsten (34) is deposited by hot-wall, low-pressure chemical vapor deposition (LPCVD). The tungsten layer (34) selectively adheres to the polysilicon layer (18) providing a low resistance path for the conductors. The tungsten layer (18) forms both a gate electrode and the low resistance interconnect lines (42) or "runs." A heat treatment may then be applied to the combined tungsten layer (34) and the polysilicon layer (16) to form a composite conductor of tungsten silicide. Thereafter the interconnect lines (42) and gate electrodes are covered by a low temperature oxide (36).

REFERENCES:
patent: 3881242 (1975-05-01), Nuttall et al.
patent: 3898105 (1975-08-01), Mai et al.
patent: 4080719 (1978-03-01), Wilting
patent: 4125854 (1978-11-01), McKenny et al.
patent: 4179311 (1979-12-01), Athanas
patent: 4290185 (1981-09-01), McKenny et al.
patent: 4305200 (1981-12-01), Fu et al.

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