Multi-level instruction boosting method using plurality of ordin

Details Multi-level instruction boosting method using plurality of ordin Multi-level instruction boosting method using plurality of ordin

1993-06-23

1996-04-02

An, Meng-Ai

Boots, shoes, and leggings

395375, 3642316, 3642318, 3642613, 3642804, 364DIG1, G06F 1516

Patent

active

055049141

ABSTRACT:
An instruction multi-level boosting method in a compiler has the step of providing a plurality of ordinary registers to act as the destination registers for access by the ordinary instructions. At least one instruction is boosted and speculatively executed. The boosting method also has the step of providing a plurality of special registers corresponding to the ordinary registers, and acting as the destination registers for access by the boosted and speculatively executed instruction. Then, at the original position of the boosted instruction, the address of at least one ordinary register used in the boosted instruction is translated into the address of at least one corresponding special register. In this way, the compiler efficiency can be incressed; the need of requiring additional registers is lowered; and the cost thereof is reduced down because no complicated duplicating circuit is needed.

REFERENCES:
patent: 4374418 (1983-02-01), Catiller et al.
patent: 4631660 (1986-12-01), Woffinden et al.
patent: 4807115 (1989-02-01), Torng
patent: 4965720 (1990-10-01), Mitchell et al.
patent: 5021993 (1991-06-01), Matoba et al.
patent: 5155817 (1992-10-01), Kishigami et al.
patent: 5224063 (1993-06-01), Matsonaga
patent: 5355460 (1994-10-01), Eickemeyer et al.
patent: 5396640 (1995-03-01), Ikenaga et al.
Michael D. Smith et al, "Boosting Beyond Static Scheduling in a Superscalar Processor", May 1990 IEEE, Stanford University, Computer System Laboratory, pp. 344-354.
Michael D. Smith et al, "Efficient Superscalar Performance Through Boosting", Oct. 1992, Computer System Laboratory, Stanford University, 1992 ACM, pp. 248-259.
Komukai Toshiba; "Twin Register Architecture for an AL Processor"; 1989 IEEE, pp. 168-173.

Affiliated with

Also associated with

Rating

Multi-level instruction boosting method using plurality of ordin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-level instruction boosting method using plurality of ordin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level instruction boosting method using plurality of ordin will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2024379