High speed serial interface between image enhancement logic and

Details High speed serial interface between image enhancement logic and High speed serial interface between image enhancement logic and

1994-12-13

1996-11-05

Heckler, Thomas M.

395891, G06F 104, G06F 9315

Patent

active

055727212

ABSTRACT:
This circuit for serializing n parallel data bits requires that the data clock, having a clock period T, be used to generate n phased clocks of the same frequency as the data clock, but varying in phase such that each phased clock is delayed T
with respect to the previous one. This can be done using a digital phase locked loop device. These n phased clocks and n parallel data bits are then input to a logic circuit which uses an n input Register and an n input multiplexer to output one data bit for each phased clock. The result is a serializer that converts parallel data to serial data without the need for generating a higher frequency clock.

REFERENCES:
patent: 4378593 (1983-03-01), Yamamoto
patent: 5122679 (1992-06-01), Ishii et al.
patent: 5457718 (1995-10-01), Anderson et al.
Digital Phased Locked Loop Application Note, Texas Instruments pp. B-1 to B-9 publication date unknown.

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