System and method for controlling split-level caches in a multi-

Details System and method for controlling split-level caches in a multi- System and method for controlling split-level caches in a multi-

1993-12-15

1996-11-05

Chan, Eddie P.

Boots, shoes, and leggings

395448, 395449, 395479, 364DIG1, 3642292, 36424345, 3642468, G06F 1216

Patent

active

055727042

ABSTRACT:
A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline. If a PM instruction is determined to be in the second level cache pipeline, the FA instructions are prevented from entering the second level cache pipeline such that execution of interventions to the second level cache is not prevented when an instruction in the second level cache may be detained to process an intervention in its behalf, thereby preventing deadlock between processing units of the computer system.

REFERENCES:
patent: 5287484 (1994-02-01), Nishii et al.

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