Testable programmable logic array

Details Testable programmable logic array Testable programmable logic array

1992-05-01

1996-04-02

Voeltz, Emanuel T.

Excavating

364489, 364490, H04B 1700

Patent

active

055047556

ABSTRACT:
A testable PLA includes a PLA comprising an AND plane and an OR plane comprising input lines, output lines, and product term lines which are grouped into at least two groups; a selector circuit for selecting one of the groups; an activation circuit for activating the selected group; a data generator for providing test data to execute a test for the PLA for the AND plane during a test operation mode, and for providing normal input data for the AND plane during a normal operation mode. The test data consisting of fixed data and variable data provided from the data generator corresponds to the distribution of devices formed at crosspoints between the product term lines of each of the selected groups and input lines.

REFERENCES:
patent: 3958110 (1976-05-01), Houg et al.
patent: 4768196 (1988-08-01), Jou et al.
patent: 4780627 (1988-10-01), Illman
patent: 4857773 (1989-08-01), Takata et al.
patent: 4959774 (1990-09-01), Davis
patent: 5121394 (1992-06-01), Russell
Hideo Fujiwara et al., "Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique", Proceedings of the IEEE International Test Conference, 1988, pp. 642-648.

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