RISC system capable of simultaneously executing data interlocked

Boots – shoes – and leggings

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3642595, 364263, 3642592, 3649476, 3649483, 3649472, 364DIG1, 395800, G06F 938

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active

052690075

ABSTRACT:
First and second instructions are simultaneously fetched from a memory to be respectively decoded by first and second instruction decoders. An instruction execution unit includes a register file, an arithmetic and logic unit, and a shifter. A first comparator compares a destination field of the first instruction with a first source field of the second instruction. The shifter produces an output in association with immediate data of the first instruction, the output being ordinarily stored in a register file. However, when both inputs of the comparator are identical to each other, the output from the shifter is supplied to an input of the arithmetic and logic unit via a bypass signal transmission path.

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