Patent
1994-06-22
1995-11-28
Bowler, Alyssa H.
395293, 395427, 395825, G06F 300
Patent
active
054716381
ABSTRACT:
A processor couples to a system bus and includes a high performance microprocessor which tightly couples to a local memory. The processor is organized at the interface level into a plurality of interface sections which include a corresponding number of state machines for enabling the simultaneous processing of a plurality of different types of transactions or requests under all conditions. One interface section is organized to include the system visible registers which are accessible for reading and writing by I/O commands received from the system bus. Another section processes memory commands received from the system bus while a further section processes read/write and I/O commands issued to the system bus by the processor.
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Bowler Alyssa H.
Bull HN Inforamtion Systems Inc.
Driscoll Faith F.
Fiul Dan
Solakian John S.
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