Multi-phase multi-access pipeline memory system

Details Multi-phase multi-access pipeline memory system Multi-phase multi-access pipeline memory system

1993-04-22

1995-11-28

Kriess, Kevin A.

Boots, shoes, and leggings

364200, 364900, 375354, 365233, 348537, G06F 938, G06F 506, H04l 700, G11C 704

Patent

active

054716071

ABSTRACT:
A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for operating each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.

REFERENCES:
patent: 4428063 (1984-01-01), Fourcade
patent: 4639866 (1987-01-01), Loo
patent: 5033001 (1991-07-01), Ibi
patent: 5206833 (1993-04-01), Lee
patent: 5220201 (1993-06-01), Kawasaki et al.
patent: 5220585 (1993-06-01), Sasaki et al.
patent: 5298998 (1994-03-01), Furumiya et al.

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