Method and system for creating and verifying structural logic mo

Details Method and system for creating and verifying structural logic mo Method and system for creating and verifying structural logic mo

1994-05-20

1996-11-05

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

055724370

ABSTRACT:
An automatic logic-model generation system operates on a behavioral description of an electronic design (e.g., a circuit, a system, etc.) to automatically generate a low-level (i.e., circuit-level) design of the electronic design, to lay out the electronic design for production in the form of an integrated circuit, and to produce logic-level models incorporating accurate timing (and delay) information. A verification process is also performed whereby the logic-level model is automatically verified for accuracy.

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