Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-04-09
2000-10-03
Phan, Trong Q.
Static information storage and retrieval
Floating gate
Particular biasing
36518522, G11C 1606
Patent
active
061282243
ABSTRACT:
A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.
REFERENCES:
patent: 5446690 (1995-08-01), Tanaka et al.
Nozoe et al., "A 256-Mb Multilevel Flash Memory with 2-MB/s Program Rate for Mass Storage Applications," IEEE, pp. 1544-1550 (1999).
Atsushi Nozoe et al., "A 256-Mb Multilevel Flash Memory with 2-MB/s Program Rate for Mass Storage Applications", 1999 IEEE Journal of Solid-State Circuits, vol. 34, No. 11, pp. 1544-1550.
Boulian Eric
Bron Michel
Marquot Alexis
Morton Bruce Lee
Stout Graham
Clingan Jr. James L.
Goddard Patricia S.
Motorola Inc.
Phan Trong Q.
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