Registers – Systems controlled by data bearing records – Time analysis
Patent
1976-09-29
1978-03-07
Atkinson, Charles E.
Registers
Systems controlled by data bearing records
Time analysis
G11C 2900, G06F 1112
Patent
active
040775658
ABSTRACT:
A main memory system includes encoder and decoder circuits. The encoder circuits are connected to receive data bits and parity bits and from them generate check code bits which are stored with the data bits during a write cycle of operation. The decoder circuits are connected to receive data and check bits read out from memory during a read cycle of operation. The decoder circuits include a plurality of decoder circuits and error locator circuits. Circuits via exclusive OR circuits generate a number of syndrome bit signals. These signals are divided into first and second groups. The first group is coded to specify which one of a number of decoder circuits comprising the error locator circuits is to be enabled in the case of an error condition. The second group of signals is coded to designate the particular data bit to be corrected by the decoder circuits. Predetermined output terminals of each of the decoder circuits representative of valid single bit data error conditions are applied to a plurality of correction circuits for modification of the data signals as specified by the decoder circuits. Additionally, signals from predetermined output terminals of certain ones of the decoder circuits representative of certain single check code bit error conditions are utilized for providing the correct parity for the data signals associated therewith.
REFERENCES:
patent: 3766521 (1973-10-01), Carter et al.
patent: 3814921 (1974-06-01), Nibby et al.
patent: 3836957 (1974-09-01), Duke et al.
patent: 3949208 (1976-04-01), Carter
patent: 4005405 (1977-01-01), West
Barlow George J.
Nibby, Jr. Chester M.
Atkinson Charles E.
Driscoll Faith F.
Honeywell Information Systems Inc.
Prasinos Nicholas
Reiling Ronald T.
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