Method for fabricating MOS transistors

Details Method for fabricating MOS transistors Method for fabricating MOS transistors

1995-07-14

1996-04-02

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437164, 437913, H01L 218234

Patent

active

055040241

ABSTRACT:
A method for fabricating a MOS transistor includes forming an oxide layer over a silicon substrate of a first conductivity type. A gate electrode is formed over the oxide layer. Ions of a second conductivity type are implanted into the silicon substrate to form lightly-doped source/drain regions. Impurity-containing spacers are formed on sidewalls of the oxide layer and the gate electrode. The spacers are thermally processed to drive impurities of a first conductivity type into the source/drain regions. Finally, ions of a second conductivity type are implanted into the substrate to form heavily-doped source/drain regions.

REFERENCES:
patent: 4697333 (1987-10-01), Nakahara
patent: 5089435 (1992-02-01), Akiyama
patent: 5170232 (1992-12-01), Narita
patent: 5179034 (1993-01-01), Mori et al.
patent: 5320974 (1994-06-01), Hori et al.
patent: 5342797 (1994-08-01), Sapp et al.

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