Self-aligned via structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Patent

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Details

257412, 257773, 257756, 257903, H01L 2348, H01L 2976, H01L 2352, H01L 2711

Patent

active

054710944

ABSTRACT:
A self-aligned via between interconnect layers in an integrated circuit allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density and improved yield. In one embodiment, self-aligned vias are used to connect first and second interconnect layers in an SRAM memory cell.

REFERENCES:
patent: 4914056 (1990-04-01), Okumura
patent: 5189506 (1993-02-01), Cronin et al.

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