Electric power conversion systems – Current conversion – Using semiconductor-type converter
Patent
1989-10-06
1991-03-19
Wong, Peter S.
Electric power conversion systems
Current conversion
Using semiconductor-type converter
363 17, 363 40, H02M 7537
Patent
active
050016210
DESCRIPTION:
BRIEF SUMMARY
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to the following pending U.S. patent applications: Ser. No. 07/295,203, now U.S. Pat. No. 4,887,272, Ser. No. 07/283,478, now U.S. Pat. No. 4,921,357, Ser. No. 07/283,479, now U.S. Pat. No. 4,930,135, and Ser. No. 07/363,516 now U.S. Pat No. 4,964,136.
Technical Field
The present invention relates to an inverter device, and more particularly, to an inverter device which includes a MOS (metal-oxide-semiconductor) transistor, more generally, a MIS (metal-insulator-semiconductor) transistor. The MIS transistor is connected in series between a d.c. power input and a load and in which the MOS transistor is driven by a drive signal having a single frequency so as to convert d.c. power into a.c. power.
The device according to the invention can be used, e.g., for a high-frequency power supply of an RF (radio frequency) pumping CO.sub.2 (carbonic acid gas) laser device or a high-frequency induction heating power supply.
BACKGROUND ART
It is generally known that, in inverter devices of the above-mentioned type, an equivalent output capacitance C.sub.OSS exists between the drain and the source of the MOS transistor. This output capacitance is a parasitic capacitance produced when the transistor is manufactured, and is the main cause of a power drop occurring during a high-frequency operation.
Namely, an electric current which charges and discharges the output capacitance flows at each switching of the MOS transistor and is consumed by the on-state resistance of the transistor, whereby the loss increases in proportion to the frequency.
Furthermore, a maximum electric power that can be input to the inverter is restricted by the peak value of a voltage applied to the source and drain of the transistor during operation. That is, the input power is limited to less than the maximum rated voltage of the transistor.
SUMMARY OF THE INVENTION
The present invention has been created in view of the above problem that a sufficient output power cannot be obtained during high-frequency operation since the allowable input power and the output efficiency of the device are low, and an object of the invention is to provide a high-power inverter device having an improved input power and efficiency but still satisfactorily practical.
To achieve the above object, according to the invention, there is provided an inverter device including input terminals for a d.c. voltage input, output terminals connected to a load, an inductance element (RFC) connected in series between at least one of the input terminals and a d.c. input power supply, and at least one MIS transistor connected in series between the input terminal and the output terminals and carrying out a switching action in response to a drive signal having a single frequency. The inverter device of the invention is characterized by comprising an inductance element connected in parallel with the output terminals and capable of a parallel resonance with a total equivalent capacitance which is the sum of an equivalent electrostatic capacitance of the inverter device as observed from the output terminals toward an input side and an equivalent electrostatic capacitance of the load.
Namely, a resonant circuit having a relatively large constant which allows the influence of various stray impedances to be neglected is provided in the device, to thereby control the output voltage waveform and provide the following effects.
First, the source-drain voltage when the transistor is switched is minimized .apprxeq.0), to thereby reduce the charge/discharge loss due to the capacitance C.sub.OSS between the source and the drain and thus improve the efficiency.
Second, the output voltage waveform is reduced until it has a small peak value relative to the mean value of the source-drain voltage, i.e., a small crest factor, whereby the mean input voltage value (.apprxeq. input d.c. voltage) is increased to thus permit an increase of the input electric power.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing a
REFERENCES:
patent: 4212053 (1980-07-01), Sichenzia
patent: 4504895 (1985-03-01), Steigerwald
patent: 4566059 (1986-01-01), Gallios et al.
patent: 4758940 (1988-07-01), Steigerwald
Fanuc Ltd
Wong Peter S.
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