BiCMOS integrated circuit with shallow n-wells

Details BiCMOS integrated circuit with shallow n-wells BiCMOS integrated circuit with shallow n-wells

1991-03-27

1992-03-24

Epps, Georgia

357 42, H01L 2702

Patent

active

050993038

ABSTRACT:
A biCMOS integrated circuit is created on a p-type semiconductor substrate on which first an n-type epitaxial layer then a p-type epitaxial layer is grown. NPN and PMOS transistors are formed in n-wells in the p-type epitaxial layer. n.sup.+ buried layers are located below the n-wells at the interface between the substrate and the n-type epitaxial layer. The n.sup.+ buried layers underlying the n-wells containing NPN transistors are surrounded by p.sup.+ buried layers that extend from the interface between the p-type and n-type epitaxial layers through the n-type epitaxial layer and into the substrate.

REFERENCES:
patent: 4597874 (1990-09-01), Soejima
patent: 4960726 (1990-10-01), Lechaton et al.
patent: 5015594 (1991-05-01), Chu et al.

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