Radiation hardened CMOS on SOI or SOS devices

Details Radiation hardened CMOS on SOI or SOS devices Radiation hardened CMOS on SOI or SOS devices

1989-01-31

1991-03-19

Prenty, Mark

357 4, H01L 2701, H01L 2712

Patent

active

050015281

ABSTRACT:
A radiation hardened CMOS transistor has a source region, drain region and channel region formed on an SOI or SOS wafer. End plugs of opposite conductivity to that of the source and drain regions are connected to the channel region. In one embodiment, the end plugs extend along opposite ends of the source region but not along the drain region. In another embodiment, the end plugs extend along opposite ends of the source region and the drain region, and the drain region includes portions adjacent the end plugs having an impurity concentration which is significantly lower than the impurity concentration of the remainder of the drain region. The transistor is surrounded by a silicon dioxide isolation region. Contact holes for establishing electrical contact are positioned over areas in which the source region interfaces with each of the end plugs, and over an area of the drain region. The end plugs are electrically tied to the source region through common metallized contacts so that radiation sensitive parasitic actions may be prevented.

REFERENCES:
patent: 4053916 (1977-10-01), Cricchi et al.
patent: 4484209 (1984-11-01), Uchida
patent: 4489339 (1984-12-01), Uchida
patent: 4809056 (1989-02-01), Shirato et al.
patent: 4906587 (1990-03-01), Blake

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