Method of via formation for the multilevel interconnect integrat

Details Method of via formation for the multilevel interconnect integrat Method of via formation for the multilevel interconnect integrat

1994-10-27

1995-11-28

Quach, T. N.

Fishing, trapping, and vermin destroying

437228, 437241, 437947, 437978, 1566531, H01L 21283, H01L 21311

Patent

active

054707935

ABSTRACT:
A method is provided for depositing a silicon nitride layer to protect and isolate underlying layers during wet etching. The silicon nitride layer maintains the integrity of interconnect leads, bond pads, and die boundaries by acting as a wet etch stop. The silicon nitride layer stops the chemicals used in a wet etch from reaching underlying layers in the integrated circuit.

REFERENCES:
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patent: 4466172 (1984-08-01), Batra
patent: 4686100 (1987-08-01), Heath et al.
patent: 4775550 (1988-10-01), Chu et al.
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5063716 (1991-11-01), Lee et al.

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