Fishing – trapping – and vermin destroying
Patent
1991-01-08
1992-03-24
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 61, 437974, 437154, 748DIG12, 748DIG147, 148 333, 148 334, H01L 2122
Patent
active
050988611
ABSTRACT:
A method for processing at least two semiconductor wafers for producing a partially processed semiconductor substrate which can be subsequently further processed utilizing conventional planar semiconductor processing techniques to achieve a complementary semiconductor structure in which a plurality of matched semiconductor elements can be formed. An embedded silicide layer in the bonded semiconductor substrate acts as a conduit for horizontally dispersing dopant during the diffusion process. The dopant subsequently up-diffuses into an adjacent silicon region forming generally uniform and shallow, buried layer regions.
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patent: 3333324 (1987-08-01), Roswell et al.
patent: 4794445 (1988-12-01), Homma et al.
patent: 4826787 (1989-05-01), Muto et al.
Ghandhi, S. K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 426-429.
Hearn Brian E.
Quach T. N.
Unitrode Corporation
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