Fishing – trapping – and vermin destroying
Patent
1989-08-04
1991-03-19
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 47, 437 60, 437919, H01L 2170, H01L 27108
Patent
active
050010786
ABSTRACT:
Island layers defined by grooves are formed on a p.sup.+ -type silicon substrate. One memory cell having a MOS capacitor and a MOSFET transistor is formed in each island layer. The MOS capacitor is buried in a groove surrounding the island layer and has a capacitor electrode insulatively provided over the bottom surface of the groove and an n.sup.- -type semiconductor layer formed in a ring-shaped manner in the side surface region of the groove and facing the capacitor electrode. The MOSFET has a ring-shaped gate electrode for in the groove to be insulatively stacked over the capacitor electrode. The gate electrode faces a p-type channel region formed in a ring-shaped manner in the side surface region of the island layer. Only a drain layer is formed in the top surface region of the island layer.
REFERENCES:
patent: 4199772 (1980-04-01), Natori et al.
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4679300 (1987-01-01), Chan et al.
patent: 4737829 (1988-04-01), Morimoto et al.
patent: 4769786 (1988-09-01), Garnache et al.
Hearn Brian E.
Kabushiki Kaisha Toshiba
Thomas T.
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