FIFO Buffer register memory utilizing a one-shot data transfer s

Details FIFO Buffer register memory utilizing a one-shot data transfer s FIFO Buffer register memory utilizing a one-shot data transfer s

1974-12-30

1976-04-27

Canney, Vincent P.

Communications: electrical

Digital comparator systems

307221C, G11C 1900, G11C 1124, H03K 2502

Patent

active

039538389

ABSTRACT:
A FIFO (first-in-first-out) buffer register in which memory data words flow in parallel from an input register through a plurality of registers towards an output register under the automatic control of a one-shot (monostable multivibrator) data transfer system. A one-shot device and a status flip-flop are associated with each individual register in the plurality of registers to asynchronously transfer a data word register-by-register from the input register to the register nearest the output register that is not occupied by a previously inputted data word. The automatic data word transfer system is initiated by either reading a word into the input register or reading a word out of the output register. Logic controls for handling the reading-in and reading-out functions operate asynchronously and independently.

REFERENCES:
patent: 3646526 (1972-02-01), Fagen et al.
patent: 3763480 (1973-10-01), Weimer
patent: 3824562 (1974-07-01), Liebowitz et al.

Affiliated with

Also associated with

Rating

FIFO Buffer register memory utilizing a one-shot data transfer s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FIFO Buffer register memory utilizing a one-shot data transfer s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FIFO Buffer register memory utilizing a one-shot data transfer s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2005671