High-speed multiplier for microcomputer used in digital signal p

Details High-speed multiplier for microcomputer used in digital signal p High-speed multiplier for microcomputer used in digital signal p

1982-02-11

1985-08-27

Smith, Jerry

Boots, shoes, and leggings

364754, G06F 752

Patent

active

045382395

ABSTRACT:
A system for real-time digital signal processing employs a single-chip mircocomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. An improved multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU; an array of static adders with carry feed-forward controlled by two-bit-at-a-time Booth's decoders, along with a dynamic carry-ripple adder, produces the one-state 16.times.16 multiply. One input to the ALU passes thorugh 0-to-15 bit shifter with sign extension.

REFERENCES:
patent: 3691359 (1972-09-01), Dell et al.
patent: 3795880 (1974-03-01), Singh et al.
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4168530 (1979-09-01), Gajski et al.
Frank S. Lee et al., "A High-Speed LSI GaAs 8.times.8 Bit Parallel Multiplier", IEEE Journal of Solid State Circuits, vol. SC-17, No. 4, Aug. '82.
Shlomo Waser, "High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing", IEEE Computer, Oct. 1978, pp. 22-24.
J. P. Beraud et al., "Parallel Multiplier", IBM Technical Disclosure Bulletin, vol. 24, No. 11B, Apr. 1982.

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