Multiple loop parallel pipelined logic simulation system

Details Multiple loop parallel pipelined logic simulation system Multiple loop parallel pipelined logic simulation system

1985-10-21

1991-01-01

Williams, Jr., Archie E.

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3649163, 3649338, 3642211, 3642323, 3642643, 3649314, 3649310, 3642318, 3642630, G06F 1516, G06F 938, G06F 928

Patent

active

049823612

ABSTRACT:
The present invention is capable of registering and reading out a logical element for which the state of the output pin changes. The system includes an input side reading out circuit for reading out the kind of logical element and the states of all the input pins thereof, a decision circuit for deciding the presence of the output pin that the status change is produced on when a logical operation is carried out according to the kind of logical element, an output side reading out circuit for reading out the information related to the logical element of the output pin producing the status change, and an exchange sending circuit for sending each information read out from the output side reading out circuit to the desired registering and reading out circuit for precise high speed logic simulation of a large scale logic circuit containing MOS-type logical elements.

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