Master-slave checking system

Details Master-slave checking system Master-slave checking system

1990-06-12

1992-10-20

Dixon, Joseph L.

Excavating

371 3, G06F 1116

Patent

active

051577801

ABSTRACT:
The system comprises a pair of error checking processors connected in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on the inputs to produce mimicked outputs, compares the mimicked outputs with the master outputs and indicates an error condition if the mimicked outputs do not equal the master outputs. A checking circuit forces a difference between the mimicked output and the master output and determines if the master slave configuration accurately determines the presence of the forced error.

REFERENCES:
patent: 3680069 (1972-07-01), Neumann et al.
patent: 4358823 (1982-11-01), McDonald et al.
patent: 4574343 (1986-03-01), Inatomi
patent: 4759019 (1988-07-01), Bentley et al.
patent: 4792955 (1988-12-01), Johnson et al.
patent: 4849979 (1989-07-01), Maccianti et al.
patent: 4903270 (1990-02-01), Johnson et al.

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