Integrated circuit with metal interconnecting layers above and b

Details Integrated circuit with metal interconnecting layers above and b Integrated circuit with metal interconnecting layers above and b

1989-04-28

1991-01-01

James, Andrew J.

Fishing, trapping, and vermin destroying

437189, 437192, 437195, 427 96, 427 97, H01L 2710, H01L 2188, H01L 21312

Patent

active

049822667

ABSTRACT:
A process for forming backside contacts includes first forming an etch stop layer (12) beneath the surface of a silicon substrate. An active circuit is then formed in the silicon surface and associated metal interconnecting layers formed on the upper surface of the substrate. A planarizing layer is then formed on the upper surface of the substrate which is operable to be connected to a mechanical support. Thereafter, the backside of the substrate is etched away up to the etch stop layer (12). The thickness of the remaining substrate between the metal layers on the upper surface and the etch stop layer is sufficiently thin that the alignment marks on the upper surface can be seen through the substrate. These alignement marks are utilized to form vias from the backside to the active elements and then deposit and pattern interconnecting layers on the backside.

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