System for fast selection of non-cacheable address ranges using

Details System for fast selection of non-cacheable address ranges using System for fast selection of non-cacheable address ranges using

1991-10-18

1992-10-20

Lee, Thomas C.

Boots, shoes, and leggings

3642434, 3642463, 364DIG1, C06F 1200, C06F 1300

Patent

active

051577747

ABSTRACT:
A fast logic system for decoding addresses for the purpose of designating areas of memory as noncacheable is disclosed. The logic system is based on a programmable array logic having as inputs selected address lines, certain switch settings, and software-selectable diagnostic settings.

REFERENCES:
patent: 4399503 (1983-08-01), Hawley
patent: 4591975 (1986-05-01), Wade et al.
patent: 4646233 (1987-02-01), Weatherfoned et al.
patent: 4719568 (1988-01-01), Carubba et al.
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5097409 (1992-03-01), Schwartz et al.
patent: 5097532 (1992-03-01), Borup et al.

Affiliated with

Also associated with

Rating

System for fast selection of non-cacheable address ranges using does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for fast selection of non-cacheable address ranges using , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for fast selection of non-cacheable address ranges using will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-200041