Priority arbitrating interface for a plurality of shared subsyst

Details Priority arbitrating interface for a plurality of shared subsyst Priority arbitrating interface for a plurality of shared subsyst

1995-06-07

1996-12-17

Lee, Thomas C.

Boots, shoes, and leggings

395301, 3642285, 3642295, 36424292, 3642301, G06F 13368, G06F 1320

Patent

active

055862659

ABSTRACT:
The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to a control circuit. The control circuit is comprised of a programmable microprocessor in bus communication with an accounting means having memory units for accounting for the postage printed by the printing unit responsive to the programming of the microprocessor. An integrated circuit includes an address decoding module means for generating a unique combination of ASIC control signals in response to a respective address placed on the bus by the microprocessor. A timer register is responsive to ones of the control signals from the address decoding module to enable writing of the timer data into the timer registers by the microprocessor. The timer unit is responsive to the timer data for timer data. Also included are a plurality of non-volatile memory units. The non-volatile memory unit responsive to other ones of the control signals from the address decoding module to enable the non-volatile memory units for writing data into the non-volatile memory unit by the microprocessor. The integrated circuit further includes a non-volatile memory access timer unit for causing the control signal from the address decoding module enabling the non-volatile memory units to stay active for a predetermined time of the non-volatile memory access timer.

REFERENCES:
patent: 4607365 (1986-08-01), Greig et al.
patent: 5081624 (1992-01-01), Beukema
patent: 5206952 (1993-04-01), Sundet et al.
patent: 5359715 (1994-10-01), Heil et al.

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