Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Patent
1987-11-30
1991-01-01
Shoop, Jr., William M.
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
341122, 341131, 341155, H03M 136
Patent
active
049821938
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention concerns improvements in or relating to a method and apparatus for analogue-to-digital conversion most especially converters (ADC's) for digital radio applications.
The requirement for an ADC for use in a radio is particularly stringent. The dynamic range, if the ADC is used to convert the incoming signal without prefiltering, must exceed 100 db and preferably be over 130 db. This calls for accuracy of greater than 17 bits and ideally more than 22 bits.
BACKGROUND ART
In digital radio applications, such converters, hitherto, have been limited in frequency to the audio range (baseband) and have therefore been preceeded by analogue down-conversion circuitry, itself a source of error in cross- and intermodulation products of the order of -100 db, i.e. at the lowest acceptable limit for the system.
In a typical arrangement, the baseband signal is sampled at an arbitrarily high rf frequency, and, after digital conversion, a large number of digitised samples accummulated to afford improved resolution or unwanted signal rejection. Such techniques have been described in the patent literature, for example: United Kingdom Patent Applications G.B. Nos. 1,532,538; 1,580,178; 2,123,233; and, 2,144,285; U.S. patent application Ser. No. 3,820,111; and, International Patent Application W.O. No. 86/02217.
DISCLOSURE OF THE INVENTION
The present invention provides a method and an apparatus for analogue to digital conversion, adapted to offer enhanced resolution, and, suitable thus for digital radio application.
In accordance with the invention thus there is provided a method of analogue to digital conversion comprising the following steps: the carrier frequency for said signal, to generate thereby a multiplicity of digitised samples, each of n - bit word length; selected thus corresponding to a common phase but a successive cycle at said carrier frequency; and, an output word of n+m bit length.
In further accordance with the invention there is provided apparatus for analogue to digital conversion, this apparatus comprising: at a rate that is integer related to input signal carrier frequency; digitised sample for each analogue sample; length; memory store to direct to each element in turn a digitised sample, each sample as thus directed corresponding to a common phase but a successive cycle at said carrier frequency; and, provide an output word of n+m bit word length indicative of an average value of the 2.sup.m samples stored therein. thus attainable using only n bit conversion quantisation at front end.
The sampling means aforesaid may be incorporated as a part of the conversion means (e.g. as in a `flash` ADC) or may be included as a dedicated sampling or sample-and-hold device.
The apparatus aforesaid may be followed by a digital filter and a digital detector. The filter may process signals either serially or in parallel if speed is requisite.
This apparatus may be applied to single sideband and amplitude modulation (AM), demodulation being performed by the action of the ADC sampling. The converter system may, with modification, also be used to process frequency modulated (FM) and frequency shift keyed (FSK) signals. Thus the sampling may be operated twice per cycle of the carrier frequency to provide in-phase and quadrature phase sampling for this purpose.
As yet further modification, the sample clock may run at a rate equal to an harmonic multiple of the selected carrier frequency, to sample thus at several samples per cycle. The data then would be fed to separate locations for respective sample phases and separate averaging performed serially or sequentially.
These and other aspects of the invention are set forth in the claims that follow hereinafter.
BRIEF INTRODUCTION OF DRAWINGS
In the drawings accompanying this specification,
FIG. 1 is a block schematic drawing showing the arrangement of the component parts of an analogue to digital converter apparatus constructed in accord with this invention;
FIG. 2 is a block schematic drawing showing memory and averaging parts of
REFERENCES:
patent: 3820111 (1974-06-01), Candy
patent: 4318086 (1982-03-01), Peck et al.
patent: 4575709 (1986-03-01), Tomlinson
patent: 4621254 (1986-11-01), Belcher
patent: 4716385 (1987-12-01), Noda et al.
patent: 4815136 (1989-03-01), Benvenuto
IEEE Int. Sol. State Ccts. Conf., Feb. 1985 (New York, U.S.), Hauser, M. W. et al., pp. 80-81, 313, "MOS ADC-Filter Combination that does not Require Precision Analog Components".
IEEE Int. Sol. State Ccts. Conf., Feb. 1980 (New York, U.S.), Black, W. C. et al., pp. 14-15, 254, "Time Interleaved Converter Arrays".
Plessey Overseas Limited
Romano Gary J.
Shoop Jr. William M.
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