Synchronous address latching for memory arrays

Details Synchronous address latching for memory arrays Synchronous address latching for memory arrays

1995-05-23

1996-12-17

Nelms, David C.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523002, 365233, 36523003, G11C 800

Patent

active

055860818

ABSTRACT:
Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.

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