Circuit for translating signal levels between a logic of the sat

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 307446, 307455, H03K 19092, H03K 19003

Patent

active

046124608

ABSTRACT:
A circuit for translating signal levels between a logic family type circuit (11) of, for example, the TTL type, and a second logic family type circuit of, for example, the ECL/CML type (12) of, for example, the ECL/CML type, in which a transit terminal (22) receives the output signals of the first logic circuit in order to translate them into input signals for the second logic circuit.
The translator circuit comprises a transistor (T1) whose base is connected to a first point (P1) at a chosen potential, which may be common ground (M), via a first forward junction (J1), and is further connected to the transit terminal (22) by a series arrangement (23) of a resistor (R1) and a second junction (J2). The circuit further has a current source (S1) connected between the supply voltage source and the emitter of the transistor T1, and a load element (Z) for the current source (S1) connected to the emitter of the transistor T1 and to a second point (P2) at a chosen potential, which may be the common ground return. One output level of the translator circuit is determined by the voltage drop in the element (Z) traversed by the current of (S1) when the transistor (T1) is cut off, while the other level is determined by the voltage at the emitter of (T1) when it is conducting.

REFERENCES:
patent: 3648064 (1972-03-01), Mukai et al.
patent: 3716722 (1973-02-01), Bryant et al.
patent: 3959666 (1976-05-01), Fett et al.
patent: 3986045 (1976-10-01), Lutz
patent: 4456838 (1984-06-01), Taguchi et al.
patent: 4477740 (1984-10-01), Takeda
patent: 4518876 (1985-05-01), Constantinescu

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