Process for creating field effect transistors having reduced-slo

Details Process for creating field effect transistors having reduced-slo Process for creating field effect transistors having reduced-slo

1990-02-16

1991-01-01

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437 28, 437 29, 437 30, 437 34, 437 56, 437 57, 437 50, 437 52, 437238, 156653, 357 236, H01L 21265, H01L 21285

Patent

active

049818104

ABSTRACT:
The present invention utilizes a wet or vapor isotropic etchback process of carefully controlled duration to create a field-effect transistor having reduced-slope, staircase-profile sidewall spacers formed from a pair of TEOS oxide layers. The spacer's reduced sidewall slope and staircase profile facilitates digit line deposition and aids in reducing the existence of short-prone polysilicon stringers.

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patent: 4902635 (1990-02-01), Imamura et al.

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