Process for and structure of high density VLSI circuits, having

Details Process for and structure of high density VLSI circuits, having Process for and structure of high density VLSI circuits, having

1978-06-06

1980-03-11

Tupman, W. C.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29590, 357 59, B01J 1700

Patent

active

041920597

ABSTRACT:
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and self-aligned contacts for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different oxidation and etch characteristics permits selective oxidation of only desired portions of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. The process and resulting structure affords inherently self-aligned gates and contacts for FET devices and conducting lines. Processing may employ conventional diffusion, oxidation, and etch techniques, although optional high energy ion implant techniques may be employed with simplification and reduction of process steps necessary for conventional diffusion techiques. Direct gate, source, drain, polysilicon line and diffused line contacts are provided. The reduction in size of individual elements and improved interconnection capabilities in accordance with the invention provide VLSI circuits having increased density and reliability.

REFERENCES:
patent: 3475234 (1969-10-01), Kerwin
patent: 3699646 (1972-10-01), Vadasz
patent: 3958323 (1976-05-01), De La Moneda
patent: 4033797 (1977-07-01), Dill

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