Method and circuit apparatus for data word error detection and c

Details Method and circuit apparatus for data word error detection and c Method and circuit apparatus for data word error detection and c

1989-11-03

1991-08-06

Baker, Stephen M.

Excavating

G11B 2018

Patent

active

050383507

ABSTRACT:
In the detection and correction of errors in the decoding of data words of a series of data word blocks each provided with check words in accordance with a Reed-Solomon code the results of the necessary calculations are precomputed and stored in permanent memory addressable by the corresponding values of syndromes and position designating numbers. In the real time correction of detection errors the predetermined correction result is obtained from the ROM in response to the generated addresses and is then exclusive-OR correlated with the corresponding data words which have been delayed by one block interval in order to correct a correctable error. The amount of ROM storage can be reduced by the use of two ROMs and several registers. Error flags for uncorrectable errors are also passed on to succeeding circuits.

REFERENCES:
patent: 4607367 (1986-08-01), Ive et al.

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