Cache with at least two fill rates

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Details

3642434, 3642329, 3642543, G06F 1300, G06F 1328

Patent

active

050382780

ABSTRACT:
During the operation of a computer system whose processor is supported by virtual cache memory, the cache must be cleared and refilled to allow the replacement of old data with more current data. The cache is filled with either P or N (N>P) blocks of data. Numerous methods for dynamically selecting N or P blocks of data are possible. For instance, immediately after the cache has been flushed, the miss is refilled with N blocks, moving data to the cache at high speed. Once the cache is mostly full, the miss tends to be refilled with P blocks. This maintains the currency of the data in the cache, while simultaneously avoiding writing-over of data already in the cache. The invention is useful in a multi-user/multi-tasking system where the program being run changes frequently, necessitating flushing and clearing the cache frequently.

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patent: 4370710 (1983-01-01), Kroft
patent: 4392200 (1983-07-01), Arulpragasam
patent: 4442488 (1984-04-01), Hail
patent: 4455602 (1984-06-01), Baxter et al.
patent: 4489378 (1984-12-01), Dixon et al.
patent: 4654819 (1987-03-01), Stiffler
patent: 4912631 (1990-05-01), Lloyd

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