Status transfer structure within a data processing system with s

Details Status transfer structure within a data processing system with s Status transfer structure within a data processing system with s

1990-03-02

1991-08-06

Anderson, Lawrence E.

Boots, shoes, and leggings

3642383, 3642473, G06F 1338

Patent

active

050382756

ABSTRACT:
A system for transferring the status information between a peripheral controller and central processing unit (CPU) is disclosed. The system utilizes three registers and an interrupt pin for determination of the presence of a STATUS VALID bit. If the STATUS VALID bit is set, then a STATUS OVERFLOW bit is set by the peripheral controller. If the STATUS VALID bit is not set, the peripheral controller updates the status information and sets the STATUS VALID bit. Through the use of this transfer system much of the complexity associated with known systems is eliminated without the concomitant loss in processing speed.

REFERENCES:
patent: 4106091 (1978-08-01), Hepworth
patent: 4325117 (1982-04-01), Parmet
patent: 4400773 (1983-08-01), Brown
patent: 4456970 (1984-06-01), Catiller et al.
patent: 4593380 (1986-06-01), Kocher
patent: 4716523 (1987-12-01), Burrus
patent: 4750113 (1988-06-01), Buggert
patent: 4901232 (1990-02-01), Harrington et al.
patent: 4910705 (1990-03-01), Boioli et al.

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