Chain configurable polycellular wafer scale integrated circuit

Details Chain configurable polycellular wafer scale integrated circuit Chain configurable polycellular wafer scale integrated circuit

1984-01-24

1984-12-18

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 100

Patent

active

044893973

ABSTRACT:
A digital memory system comprises a wafer full of uncomitted but interconnectable memory cells and a controller acting as an interface between the wafer and a host system. Each cell comprises input logic to allow coupling thereto from just one other neighboring cell and output logic allowing a cell to be commanded by the controller to couple to any selectable one other neighboring cell not already so coupled to. The controller accesses the wafer via a port and successively tests and couples cells from the port to form a chain of memory cells. Each cell comprises a plurality of individually selectably usable data storage loops and allows a cell to be used even if the loops are not fully functional by the provision of through-passing data transfer path.

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Aubusson et al., "Water-Scale Integration-A Fault-Tolerant Procedure" IEEE Journal of Solid-State Circuits, vol. SC-13, No. 3, Jun. 1978, pp. 339-344.
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Egawa et al., "Memory Technology", 1979 IEEE International Solid State Circuits Conference, Feb. 1979, pp. 18-19.

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