Method and apparatus for forming integrated circuit layers

Details Method and apparatus for forming integrated circuit layers Method and apparatus for forming integrated circuit layers

1993-01-26

1994-11-22

Bueker, Richard

Coating apparatus

Gas or vapor deposition

With treating means

118715, 118723E, C23C 1600

Patent

active

053665570

ABSTRACT:
A method of forming a planarized or smoothed dielectric or other material layer upon a partially fabricated integrated circuit is disclosed. Conventional planarization techniques involve deposition of a dielectric or other material layer followed by anisotropic etchback. Unfortunately, some commercial equipment tends to etch the center of the wafer faster than the edges. The disclosed process forms a layer which is thicker in the central region than the edge region. Thus, when the disclosed process is followed by a conventional etchback, a planar dielectric or other material layer over the entire wafer is formed. Other aspects of the invention include processes and apparatus for producing smooth deposition and etching by control of the impedance of the etching and/or chemical precursor gases.

REFERENCES:
patent: 5000113 (1991-03-01), Wang
patent: 5186756 (1993-02-01), Benko

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