Patent
1975-06-25
1977-05-10
Wojciechowicz, Edward J.
357 68, 357 55, 357 52, H01L 2348, H01L 2934, H01L 2906, H02B 104
Patent
active
040231976
ABSTRACT:
An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularities at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns. These opposite metallization patterns are also respectively separated by covering layers of dielectric material.
REFERENCES:
patent: 3622384 (1971-11-01), Davey et al.
patent: 3936865 (1976-02-01), Robinson
IBM, Tech. Bul., vol. 14, No. 9, Feb. 1972, Anderson et al., p. 2581.
Magdo Ingrid E.
Magdo Steven
IBM Corporation
Kraft J. B.
Wojciechowicz Edward J.
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