Programmable tiles

Boots – shoes – and leggings

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Details

364489, 364488, G06F 1560

Patent

active

051576180

ABSTRACT:
Disclosed is a set of functional components (tiles), consisting in part of subgate elements, which, by their design, facilitate the creation of dense integrated circuits, without forfeiting the capability of modifying the functionality of individual tiles by late mask programming techniques. Overall densities approaching those obtained with hand-crafted, custom designs can be obtained in part because such components are designed to be tiled throughout a storage logic array, permitting the creation of orthogonal logic gates as well as individual gates (and more complex functions) the functionality of which is distributed horizontally, vertically and even in a zigzag fashion. Moreover, the transition time from prototype to high volume manufacturing is reduced significantly due to the ease with which even complex functions can be repaired and enhanced.

REFERENCES:
patent: 4641108 (1987-02-01), Gill, Jr.
patent: 4644187 (1987-02-01), Haji
patent: 4688072 (1987-08-01), Heath et al.
patent: 4949275 (1990-08-01), Nonaka
"LORES-Logic Reorganization System" by Nakamura et al., IEEE 15th Design Automation Conference, 1978, pp. 250-260.
"On the Design of Easily Testable and Reconfigurable VLSI processor arrays" by J. H. Kim et al., Workshop on Designing for Field, Oxford, 1982.
"A Cost Oriented Redundancy Model for Defect-Tolerant VLSI/WSI Systems" by U. Ramacher, Adam Hilger, Jan. 1988.
W. A. M. Van Nolje et al., "Advanced CMOS Gate Array Architecture Combining Gate Isolation and Programmable Routing Channels", IEEE Journal of Solid-State Circuits, vol. SC-20, Apr. 1985, pp. 469-480.

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