Register group circuit for data processing system

Details Register group circuit for data processing system Register group circuit for data processing system

1994-11-23

1997-02-25

Pan, Daniel H.

Boots, shoes, and leggings

395307, 395308, 364DIG1, 364DIG2, 365220, G06F 1320, G06F 1340

Patent

active

056067097

ABSTRACT:
A general-purpose register group circuit provided in a data processing system includes a plurality of register groups connected to a first bus and a second bus, data being written into the plurality of register groups via the first bus according to a first control signal and being read therefrom via the second bus according to a second control signal. An output register group is connected to the plurality of register groups via the first and second buses. The data read from the plurality of register groups is written into the output register group according to a third control signal, and data read from the output register group is sent to an inner bus of the data processing system according to a fourth control signal. Each of the plurality of register groups includes a plurality of unit registers, each of which registers includes a first part for setting the second bus to either a high-impedance state or a reference level according to data latched therein and the second control signal. The output register group includes a second part for driving the inner bus according to a state of the second bus.

REFERENCES:
patent: 4725987 (1988-02-01), Cates
patent: 5197035 (1993-03-01), Ito
patent: 5333282 (1994-06-01), Maejima et al.
patent: 5341506 (1994-08-01), Nohmi et al.

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