Digital neural network computation ring

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395 11, 395800, G06F 1518

Patent

active

052089002

ABSTRACT:
An artificial neural network is provided using a digital architecture having feedforward and feedback processors interconnected with a digital computation ring or data bus to handle complex neural feedback arrangements. The feedforward processor receives a sequence of digital input signals and multiplies each by a weight in a predetermined manner and stores the results in an accumulator. The accumulated values may be shifted around the computation ring and read from a tap point thereof, or reprocessed through the feedback processor with predetermined scaling factors and combined with the feedforward outcomes for providing various types neural network feedback computations. Alternately, the feedforward outcomes may be placed sequentially on a data bus for feedback processing through the network. The digital architecture includes a predetermined number of data input terminals for the digital input signal irrespective of the number of synapses per neuron and the number of neurons per neural network, and allows the synapses to share a common multiplier and thereby reduce the physical area of the neural network. A learning circuit may be utilized in the feedforward processor for real-time updating the weights thereof to reflect changes in the environement.

REFERENCES:
patent: 4156798 (1979-05-01), Doelz
patent: 4193115 (1980-03-01), Albus
patent: 4905143 (1990-02-01), Takahashi et al.
patent: 4941122 (1990-07-01), Weideman
patent: 5038282 (1991-08-01), Gilbert et al.
patent: 5050065 (1991-09-01), Dartois et al.
patent: 5091864 (1992-02-01), Tsaji et al.
Hammerstrom, D., "A VLSI Architecture for High-Performance, Low-Cost, On-chip Learning", II 537-II 544, Feb. 1990.
Fu et al., "A Universal Digital VLSI Design for Neural Networks", IJCNN, Jun. 1989.
Hamacher et al., Computer Organization 2nd ed, McGraw-Hill Book Co., 1984, pp. 288-308, 131-137.
Pacheco et al., "A Simple VLSI Architecture for Neurocomputing", Neural Networks, vol. (1), 1988, p. 398.
Kung et al., "A Unified Systolic Architecture for Artificial Neural Networks", Jour. Parallel & Dist. Computing 6, 1989, pp. 358-387.
Treleaven et al., "VLSI Architectures for Neural Networks", IEEE Micro, Dec. 1989, pp. 8-27.
Suzuki et al., "A Study of Regular Architectures for Digital Implementation of Neural Networks", IEEE Int'l. Symp. Ckts & Sys, May 1989, 82-85.

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