Multi-level symbol synchronizer

Details Multi-level symbol synchronizer Multi-level symbol synchronizer

1991-04-08

1993-05-04

Kuntz, Curtis

Pulse or digital communications

Repeaters

Testing

375113, H03K 1324

Patent

active

052088332

ABSTRACT:
A symbol synchronizer for a communication receiver receiving multi-level data signals includes a reference clock generator for generating a reference clock signal having a predetermined time period, a state change detector for detecting state changes occurring within the received multi-level data signals over the predetermined time period to enable determining a time location corresponding to the detected state change wherein the time locations are assigned predetermined numeric values corresponding to the time locations determined, an accumulator for accumulating a time location for the time locations selected, and a phase adjusting circuit which is responsive to the time location count for adjusting the phase of the reference clock signal relative to the received multi-level data signal.

REFERENCES:
patent: 3775688 (1973-11-01), Hinashita et al.
patent: 4571735 (1986-02-01), Furse
patent: 4965814 (1990-10-01), Yoshida et al.
patent: 5052031 (1991-09-01), Molloy
patent: 5065384 (1991-11-01), Yokogawa

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