Patent
1997-06-03
1998-05-26
Ray, Gopal C.
395733, 395737, 395741, G06F 1326
Patent
active
057581690
ABSTRACT:
A multi-processor system includes an interrupt bus used for arbitrating among eligible processors to determine which processor is to service of an interrupt request. The interrupt bus comprises wired-OR connection data lines that are used for arbitration. A local interrupt controller that handles the acceptance of interrupt request messages on the interrupt bus is associated with each processor. To minimize interruption of high priority tasks, interrupts can be accepted by the processor in the system that is currently running the lowest priority task. An arbitration protocol governs the interrupt bus and determines the lowest priority processor. The arbitration protocol includes choosing one among the lowest priority processors by means of a random priority scheme that uses an arbitration ID that is updated with each message.
REFERENCES:
patent: 4648029 (1987-03-01), Cooper et al.
patent: 5067071 (1991-11-01), Schanin et al.
patent: 5077662 (1991-12-01), Hutson
patent: 5179707 (1993-01-01), Piepho
patent: 5201051 (1993-04-01), Koide
patent: 5212796 (1993-05-01), Allison
patent: 5265215 (1993-11-01), Fukuda et al.
patent: 5307466 (1994-04-01), Chang
patent: 5535395 (1996-07-01), Tipley et al.
patent: 5553248 (1996-09-01), Melo et al.
patent: 5553310 (1996-09-01), Taylor et al.
Carson David
Nizar P. K.
Intel Corporation
Ray Gopal C.
LandOfFree
Protocol for interrupt bus arbitration in a multi-processor syst does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Protocol for interrupt bus arbitration in a multi-processor syst, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Protocol for interrupt bus arbitration in a multi-processor syst will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1976879