Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Patent
1998-04-21
2000-10-24
Maung, Zarni
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
712217, 712218, 712228, G06F 930
Patent
active
061382310
ABSTRACT:
A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
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Deosaran Trevor A.
Garg Sanjiv
Iadonato Kevin R.
Maung Zarni
Najjan Saleh
Seiko Epson Corporation
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